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Byte-Controlled Transfers
Byte-controlled write transfers do not suffer the same handicap as read transfers. The core always validates the write by
setting the four or eight WR_BE_NOW signals with each data transfer. Figure 6-18 shows a write transfer that writes
byte 0 on the first transfer and then all four bytes on the following transfers. Some systems may require that I/O accesses
be verified for legality, i.e., AD[1:0] and CBEN[3:0] are consistent. In this case, the backend should wait until
BYTE_VALN is active (LOW) and then verify MEM_ADD[1:0] and BYTE_VALN[3:0] for consistency (PCI
Specification 3.2.2.1). If okay, the backend should assert WR_BE_RDY or RD_STB_IN; otherwise, it should assert the
ERROR input to cause a Target abort.
cycle
0
1
2
3
4
5
6
7
8
clk
framen
cben[3:0]
7
E
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
wr_cyc
wr_be_rdy
0
wr_be_now[3:0]
1
F
mem_add[15:0]
mem_data_out[31:0]
0000
0
0004
1
0008
2
000C
3
Figure 6-18 · Byte Burst Write Cycle
v4.0
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